The present invention relates to a communication system in which a plurality of nodes are connected onto a multiplex transmission line of communication data having a frame structure formed by a plurality of time slots and a plurality of packets, and more particularly to a communication system suitable for receiving communication data while converting these data into continuous data.
As to communication data flowing in a communication transmission line, data are arranged in reserved time slots. A communication terminal equipment is connected to every node. A buffer is provided in each node, and the buffer takes in data from the transmission line at a predetermined write rate every time the reserved time slot arrives so as to store the data in a memory once. Then, the data are read continuously from the memory at a read rate slower than the write rate and sent to the communication terminal equipment.
The data from the transmission line stay in the buffer once before they are sent to the communication terminal equipment. This residence time becomes the delay time of data transmission among communication terminal equipment. The shorter the residence time is, the shorter the data transmission time becomes, which is preferable.
It is referred to as underflow that there is no accumulated data in the memory of the buffer and a state of being unable to read data out of the memory is continuous. Conventionally, when underflow is generated, it has been waited to read out the data until data are accumulated sufficiently in a memory of a buffer. The queuing time has become the residence time of the data, thus making the time required for data transmission to the communication terminal longer.
A control method of a buffer in case underflow is generated is disclosed in Japanese patent un-examined publication No. JP-A-64-41541 filed by FUJITSU LTD. on Aug. 8, 1987. In this buffer control system, a counter for counting every time underflow is generated in a receiving buffer is provided, and data are read out of the receiving buffer after storing count values worth of data quantity are stored once in the receiving buffer.
In the techniques disclosed in this official gazette, there has been such a problem that the residence time of data in the buffer is required by the count value portion of the buffer number set in the counter, and the transmission delay time becomes longer in accordance therewith.
A method of circuit switching in a token ring Local Area Network (LAN) is disclosed in Japanese patent un-examined publication No. JP-A-62-266943 filed by Mitsubishi Electric Corp. on May 14, 1986. According to the invention set forth in this official gazette, data are transferred after accumulating the data in a buffer for a certain period of time, and a problem of transmission delay due to the residence time of data is posed.
A multichannel packet receiving system is disclosed in Japanese patent un-examined publication No. JP-A-62-266946 filed by FUJITSU LTD. on May 14, 1986. According to the invention set forth in this official gazette, dummy data are accumulated in a buffer in advance, and the quantity of those dummy data (offset) is varied in accordance with communication distance in order to absorb arrival fluctuation of the data.
A present communication system is disclosed in Japanese patent un-examined publication No. JP-A-2-14644 filed by NEC Corp. on Jun. 30, 1988. According to the invention set forth in this official gazette, flow control among nodes in units of packet is performed.
A buffer memory circuit for packet transmission is disclosed in Japanese patent un-examined publication No. JP-A-2-111137 filed by FUJITSU LTD. on Oct. 20, 1988. According to the invention set forth in this official gazette, read and write addresses are moved, respectively, when overflow and underflow are generated.
A load control system of a packet exchange is disclosed in Japanese patent un-examined publication No. JP-A-2-1671 filed by TOSHIBA CORP. on Jun. 30, 1988. According to the invention set forth in this official gazette, when the data quantity in a buffer exceeds a certain threshold, conflict is made to generate intentionally on a bus so as to delay data transmission to the buffer temporarily.